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RT9912A 1 ds9912a-01 april 2011 www.richtek.com marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. ordering information pin configurations (top view) wqfn-24l 4x4 multi-channel power management ic for portable device general description the RT9912A is a multi-channel power management ic providing power conversion and system power manage- ment functions for one or two alkaline battery powered portable handheld device. the RT9912A integrates one high efficiency synchronous buck regulator, one high efficiency boost regulator, one linear regulator and one adjustable voltage detector for reset function. features z z z z z 300ma sync. step down converter for v core z z z z z 300ma sync. step up converter for io and memory z z z z z high efficiency up to 92% z z z z z low dropout linear regulator z z z z z adjustable voltage detector for reset function z z z z z current limit protection z z z z z thermal shutdown protection z z z z z low operation current consumption z z z z z small 24-lead wqfn package z z z z z rohs compliant and halogen free applications z dsc z portable multimedia player z gps note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. vdd1 fb1 ensw psw nc enbst fb4 vdd4 enbuk vdd3 fb3 vout3 fb2 pgnd2 lx2 vdd2 pvdd2 pgnd1 gnd vout1 lx1 vbat ct reset 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8 9 10 12 14 13 24 22 23 11 gnd 25 RT9912A package type qw : wqfn-24l 4x4 (w-type) lead plating system g : green (halogen free and pb free)
RT9912A 2 ds9912a-01 april 2011 www.richtek.com typical application circuit enbuk enbst v out2 psw vdd3v3_io v out3 power on sequence : v out2 vdd3v3_io v out3 vout1 lx1 fb1 vdd1 vbat enbst RT9912A pgnd1 psw fb4 ct vdd4 gnd enbuk vout3 pvdd2 1 17 6 11 18 14 20 15 22 16 10 8 2 24 4 19, exposed pad (25) pgnd2 fb3 vdd2 vdd3 v bat v out1 3.3v vdd3v3_io vdd3 23 21 12 13 3 ensw c3 c4 c6 c7 c9 d1 r3 r4 r1 r2 r5 r6 l1 q1 1nf 1m 120k 1uf 1uf 1uf 4.7uh 10uf 1.2m 120k 2.2pf 22uf 7 9 lx2 fb2 c10 r7 r8 l2 4.7uh 1.6m 330k 100pf 10uf 590k 390k c8 1nf 4.7uf 22uf c1 c2 c5 c11 c16 c13 22nf v out3 3v c12 1uf vdd2 v out2 1.8v v out2 vdd3v3_io reset
RT9912A 3 ds9912a-01 april 2011 www.richtek.com function block diagram ch1 syn-boost pfm pgnd1 pgnd1 pvdd1 pvdd1 ch2 syn-buck pfm pgnd2 pgnd2 pvdd2 pvdd2 ch3 ldo regulator vdd3 fb3 ch4 reset reset signal delay vdd4 thermal protection pgnd1 gnd vout1 lx1 vout3 fb2 pgnd2 lx2 vdd2 pvdd2 ct vdd1 fb1 ensw psw enbst fb4 vdd4 vdd3 fb3 vbat vdd1 ch1 power ready enbuk ldook enldo reset
RT9912A 4 ds9912a-01 april 2011 www.richtek.com pin no. pin name pin function 1 vdd1 ch1 power input pin. 2 fb1 ch1 feedback input pin. 3 ensw load disconnect enable pin. 4 psw load disconnect p-mosfet gate drive pin. 5 nc no internal connection. this pin must be floating. 6 enbst boost enable pin. 7 fb2 ch2 feedback input. 8 pgnd2 power ground for ch2. 9 lx2 ch2 switch node. 10 pvdd2 ch2 power input pin. 11 vdd2 ch2 power input pin for analog. 12 vout3 ch3 output voltage. 13 fb3 ch3 feedback input. 14 vdd3 ch3 power input pin. 15 enbuk buck enable pin. 16 reset reset pulse output, negative pulse. 17 vdd4 ch4 power input pin. 18 fb4 ch4 feedback input. 19, exposed pad (25) gnd analog ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 20 ct external delay adjust pin. 21 pgnd1 power ground for ch1. 22 vbat battery power input pin. 23 lx1 ch1 switch node. 24 vout1 ch1 output voltage. functional pin description
RT9912A 5 ds9912a-01 april 2011 www.richtek.com absolute maximum ratings (note 1) z supply voltage, v dd1 , v dd2 , v dd3 , v dd4 , pv dd2 -------------------------------------------------------------------- ? 0.3v to 6.5v z lx1 and lx2 pin switch v oltage ---------------------------------------------------------------------------------------- ? 0.3v to 6.5v z other i/o pin voltage ------------------------------------------------------------------------------------------------------ ? 0.3v to 6.5v z power dissipation, p d @ t a = 25 c wqfn-24l 4x4 ------------------------------------------------------------------------------------------------------------- 1.852w z package thermal resistance (note 2) wqfn-24l 4x4, ja -------------------------------------------------------------------------------------------------------- 54 c/w wqfn-24l 4x4, jc ------------------------------------------------------------------------------------------------------- 7 c/w z junction temperature ------------------------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------- 200v electrical characteristics (v dd1 = v dd2 = v dd3 = v dd4 = 3.3v, t a = 25 c, unless otherwise specified) parameter symbol test condition min typ max units supply voltage minimum operating input voltage r l = 3k -- -- 1.7 v minimum startup voltage (boost) v s t r l = 3k -- 0.8 1.1 v vdd 1 operating voltage v dd 1 1.7 -- 5 v vdd 2 operating voltage v dd 2 vdd2 , pvdd2 pin voltage 1.7 -- 5 v vdd 3 operating voltage v dd 3 2.5 -- 5 v vdd 4 operating voltage v dd 4 1.5 -- 5 v vdd 1 over voltage protection 5.1 6 6.5 v supply current shutdown supply current i off v enbst = v ensw = 0v v dd4 = 0v = v dd3 -- -- 10 ua bo ost su pply c urre nt i vdd1 v dd1 = 3.3v, v fb1 = 0 .9v v enbst = v ensw = 3.3v v out1 = 3.3v v dd2 = v dd 3 = v dd4 = 0v (no switching) -- 45 70 ua buck supply current i vdd2 v dd2 = 3.3v, v fb2 = 0 .9v v enbst = v ensw = 0v v dd1 = v dd 3 = v dd4 = 0v (no switching) -- 85 140 ua to be continued recommended operating conditions (note 4) z supply input voltage, v bat ----------------------------------------------------------------------------------------------- 1.7v to 5v z junction temperature range --------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range --------------------------------------------------------------------------------------------- ? 40 c to 85 c
RT9912A 6 ds9912a-01 april 2011 www.richtek.com parameter symbol test condition min typ max units ldo supply current i vdd3 v dd3 = 5 v v enbst = v ensw = 0v v dd1 = v dd 2 = v dd4 = 0v -- 90 130 ua voltage detector supply c urrent i vdd4 v dd4 = 3. 3v v enbst = v ensw = 0v v dd1 = v dd 3 = v dd3 = 0v -- 10 -- ua feedback voltage (ch1, ch2) feedback voltage v fb fb1, fb2 0.292 0.3 0.312 v line regulation of feedback voltage of ch1 v fb i l = 3 0m a, v out = 2.8v v bat = 0.9 to 1.5v -- -- 8 mv power switch ch1 on resistance of mosfet r ds(on) n-mosfet, v out1 = 3 .3v -- 200 400 m p-m osfet, v out1 = 3.3v ch1 current limitation (note 5) -- 1.2 -- a ch2 on resistance of mosfet r ds(on) n-mosfet, v dd2 = 3.3v -- 320 450 m p-m osfet, v dd 2 = 3.3v -- 400 560 m ch2 current limitation p-mosfet -- 0.6 -- a voltage d etector feedback voltage v fb4 fb4 falling edge 0.292 0.3 0.308 v threshold hysteresis refer to fb4 -- 25 -- mv reset output current n-mosfet, v dd4 = 3 .3v, v ds = 0.5v -- 3 -- ma p-m osfet, v dd 4 = 3.3v, v ds = -0.5v ct pin threshold voltage v ct v dd4 = 3.3v 0.65 0.8 1 v ct pin output current i c t -- 1 -- ua linear regulator output voltage accuracy i l = 1ma, v out3 = 3.5v, 3.3v, 3v ? 2 -- +2 % feedback voltage v fb3 -- 1.2 -- v current limit i out3_l im 400 600 -- ma dropout voltage v dr op i vout3 = 200ma -- 0.3 0.4 v line regulation v line v dd3 = (v out3 + 1v) to 5.5v i out3 = 1 ma -- -- 0.5 % load regulation v out3 i out3 = 50ma to 200ma v dd3 = 4 .8v, v out3 = 3.3v -- -- 30 mv control enld o input high level threshold v dd1 = 2.8v -- -- 1.1 v to be continued
RT9912A 7 ds9912a-01 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for the package. note 3. devices are esd sensitive. handlin g precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test condition min typ max units enldo input low level threshold v dd1 = 2.8v 0.4 -- -- v enbst/ ensw input high level threshold v bat = 1v -- -- 0.7 v enbst/ ensw input low level threshold v bat = 1v 0.2 -- -- v enbst pull low current -- 1 -- ua enbuk pull low current -- 1 -- ua thermal protection thermal shutdown t sd -- 160 -- c thermal shutdown hysteresis t sd -- 10 -- c
RT9912A 8 ds9912a-01 april 2011 www.richtek.com typical operating characteristics ch1 efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 output current (a) efficiency (%) v in = 3v v in = 2.5v v in = 1.8v v out = 3.3v ch2 efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 output current (a) efficiency (%) v in = 3.3v v in = 2.5v v in = 2v v out = 1.8v ch1 output voltage vs. output current 3.10 3.15 3.20 3.25 3.30 3.35 3.40 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 output current (a) output voltage (v) v in = 3.3v v in = 2.5v v in = 1.8v v out = 3.3v ch1 output voltage vs. temperature 2.0 2.3 2.5 2.8 3.0 3.3 3.5 3.8 4.0 -40-20 0 20406080100120 temperature output voltage (v) v in = 3v v in = 2.5v v in = 1.8v v out = 3.3v, no load ( c) ch2 output voltage vs. output current 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 output current (a) output voltage(v) v in = 4.2v v in = 3.3v v in = 2.5v v out = 1.8v ch2 output voltage vs. temperature 1.60 1.65 1.70 1.75 1.80 1.85 1.90 -40 -20 0 20 40 60 80 100 120 temperature output voltage (v) v in = 3.3v v in = 2.5v v in = 2v v out = 1.8v, no load ( c)
RT9912A 9 ds9912a-01 april 2011 www.richtek.com time (5ms/div) fb4 (200mv/div) v dd4 = 1v reset power on reset (1v/div) time (5ms/div) fb4 (200mv/div) v dd4 = 1v reset power off reset (1v/div) ldo dropout voltage vs. output current 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 output current (ma) dropout voltage (mv) v out = 3v ldo output voltage vs. input voltage 2.90 2.93 2.95 2.98 3.00 3.03 3.05 3.08 3.10 3.3 3.55 3.8 4.05 4.3 4.55 4.8 5.05 5.3 input voltage (v) output voltage (v) i out = 200ma ch3 output voltage vs. temperature 2.7 2.8 2.9 3.0 3.1 3.2 3.3 -40 -20 0 20 40 60 80 100 120 temperature output voltage (v) ( c) v in = 4.5v v in = 3.9v v in = 3.3v v out = 3v, no load ch3 output voltage vs. output current 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 output current (a) output voltage (v) v in = 4.5v v in = 3.9v v in = 3.3v v out = 3.3v
RT9912A 10 ds9912a-01 april 2011 www.richtek.com application information RT9912A is a four-channel power management ic (pmic) including one step-up dc-dc converter (boost), one step- down dc-dc converter (buck), one low dropout regulator (ldo) and one voltage detector. for optimizing the application of portable hand-held system with one or two alkaline battery, several special logics are designed in this chip. an external p-mosfet is also needed for load- disconnected function. step-up dc-dc converter (boost) the step-up dc-dc convert can start up even with the input voltage as low as 0.8v and operates with the input voltage down to 0.7v. the cost of system is reduced by the internal synchronous rectifier from eliminating an external schottky diode. the efficiency of light load is improved by the pulse frequency modulation mode (pfm) low quiescent current 30ua. the efficiency of heavy load is also maintained by the internal synchronous rectifier with resistance low to 0.2 . the step-up dc-dc converter is designed as a bootstrapped structure. as the chip is in the start-up period, a low voltage start-up circuit will pull the output voltage to a higher voltage (~1.5v). after the output voltage reaches a certain level, the main dc-dc circuitry will keep working to pull the output voltage to the expected value set by output divided resistor. the control scheme of the step- up dc-dc converter is pulse frequency modulation mode (pfm) with constant-on-time and minimum-off-time. this scheme can keep high efficiency during a wide load range. an internal soft-start is also included in the step-up dc- dc converter to limit the inrush current to less than a half of the ocp level. as the enbst is pulled low, the step-up dc-dc converter will enter shutdown mode and all function will be disabled. as the ensw is pulled high, the psw will be pulled low when the output of the step-up dc-dc converter is ready (soft-start is finished). an external p-mosfet is needed to be a load-disconnected switch. the psw is a signal to control the external p-mosfet. all loadings of the system should be connected to the drain pin of the p-mosfet to prevent the step-up dc-dc converter start- up in heavy load condition. the maximum duty (d) of the step-up dc-dc converter is around 50% so that the maximum output voltage is ideally to be v in / (1-d) = 2 x v in . actually, some voltage will drop on the internal n-mosfet and inductor. therefore, the maximum output voltage will be lower than the ideal value and to be 2 x v in . the function of r9 and c14 is preventing the charge sharing issue from the capacitor in q1's source pin to the capacitor in q1's drain pin. if the capacitor in q1's source pin is 10 times larger than the capacitor in q1's drain pin, r9 and c14 can be removed. step-down dc-dc converter (buck) the step-down dc-dc convert can reduce the cost of system by the internal synchronous rectifier from eliminating an external schottky diode. the light load efficiency is improved by the pulse frequency modulation mode (pfm) and internal synchronous rectifier. for heavy load, the efficiency is maintained by the internal synchronous rectifier with the resistance low to 0.4 . the control scheme of the step-down dc-dc converter is pulse frequency modulation mode (pfm) with over-current- protection (ocp) and minimum-off-time. this scheme can keep high efficiency during a wide load range. an internal soft-start is also included in the step-down dc-dc converter to limit the inrush current less than a half of ocp level. this step-down converter can operate in low-drop mode and its output voltage depends on the voltage drop cross the internal p-mosfet and inductor. normally, the value is near vdd2 as the esr of inductor is 0.1 and 60ma loading. the minimum output voltage is 0.6v, which is decided by the operation range of the internal circuit. low dropout regulator (ldo) the low dropout regulator can regulate the output voltage by setting the external resistor of fb3. an internal compensation structure is designed for keeping stability as wide range output capacitor and wide range loading. the voltage detector is a comparator with reference to detect the voltage of fb4.
RT9912A 11 ds9912a-01 april 2011 www.richtek.com figure 1. detector delay time inductor selection to select suitable inductance value is very important for optimal performance. for boost converter, the control method is constant on time and minimum off time. if the inductance is low, it will cause effects of high in ductor current and high output voltage ripple. the inductance value can be calculated by following formula. where l min = minimum inductance v in(max) = maximum input voltage t on = 0.75us i lim(min) = 0.8a a 4.7uh inductor is recommended for typical application. for buck converter, a 4.7uh inductor is recommended when v in is less than 2.6v. in addition, make sure the inductor saturation current rating should be greater than the inductor peak current. input capacitor selection for better input bypassing, low-esr ceramic capacitor is recommended for better performance. a 10uf input capacitor is sufficient and it is flexible to reduce the value for a lower output power requirement. output capacitor selection for lower output voltage ripple, low-esr ceramic capacitor is recommended. the output voltage ripple consists of two components : one is the pulsating output ripple current flowing through the esr, and the other is the capacitive ripple caused by charging and discharging. for ceramic capacitor, the voltage ripple value is approximated by : for boost converter, calculate the minimum output capacitance as the following formula : ch4 detecter delay time 0 20 40 60 80 100 120 0 102030405060708090100 capacitance (nf) delay time (ms) to place the resistor-divider as close as possible to chip can reduce noise sensitivity. voltage detector the RT9912A integrates a voltage detector with push-pull output. the voltage detector senses vdd3v3_io through a resistor divider and compares it with internal 0.3v reference voltage. when the sensed voltage is lower than the reference voltage, the reset pin output logic low signal for system access. connecting a capacitor from the ct pin to gnd can set the detect delay time according to figure 1. the maximum output voltage for ldo depends on the voltage drop cross the internal p-mosfet. normally, the value is (vdd3 ? 0.4v) as 200ma loading. the minimum output voltage is 1.6v, which is decided by the working range of the internal circuit. output voltage setting the regulated output voltage can be calculated following formula : out fb r1 v = v 1 r2 ?? + ?? ?? in(max) on min lim(min) vt l v ripple ripple_c v v ? 2 peak out repple_c l0.5i c v
RT9912A 12 ds9912a-01 april 2011 www.richtek.com for buck converter, calculate the minimum output capacitance as the following formula : thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT9912A, where t j(max) is the maximum junction temperature of the die (125 c) and t a is the maximum ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wqfn-24l 4x4 packages, the thermal resistance ja is 54 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (54 c/w) = 1.852w for wqfn-24l 4x4 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT9912A packages, the figure 2 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. figure 2. derating curves for RT9912A packages 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wqfn-24l 4x4 four layers pcb layout considerations for the best performance of the RT9912A, the following pcb layout guidelines must be strictly followed. ` place the input and output capacitors as close as possible to the input and output pins respectively for good filtering. ` keep the main power traces as possible as wide and short. ` the switching node area connected to lx and inductor should be minimized for lower emi. ` place the feedback components as close as possible to the fb pin and keep these components away from the noisy devices. ` connect the gnd and exposed pad to a strong ground plane for maximum thermal dissipation and noise protection. 2 out(max) out(max) peak out repple_c i i1 i c fv ?? ? ?? ??
RT9912A 13 ds9912a-01 april 2011 www.richtek.com figure 3. pcb layout guide lx should be connected to inductor by wide and short trace, keep sensitive components away from trace. input/output capacitors must be placed as close as possible to the input/ output pins. place the feedback components as close as possible to the fb pin and keep away from noisy devices. gnd vdd1 fb1 ensw psw nc enbst fb4 vdd4 enbuk vdd3 fb3 vout3 fb2 pgnd2 lx2 vdd2 pvdd2 pgnd1 gnd vout1 lx1 vbat ct reset 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8 9 10 12 14 13 24 22 23 11 gnd 25 gnd r6 c8 r5 r4 r3 pgnd c3 pgnd c2 vdd3v3_io vdd3v3_io c4 l1 c5 d1 c23 c7 gnd gnd c1 r1 c6 q1 c16 vdd3v3_io v out1 3.3v pgnd gnd r8 r7 c10 l2 c11 pgnd c9 c12 v out3 3.3v pgnd v bat pgnd v out1 3.3v v out2 1.8v pgnd connect the exposed pad to a ground plane.
RT9912A 14 ds9912a-01 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com a a1 a3 d e d2 e2 l b e 1 see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.950 4.050 0.156 0.159 d2 2.300 2.750 0.091 0.108 e 3.950 4.050 0.156 0.159 e2 2.300 2.750 0.091 0.108 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 24l qfn 4x4 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 outline dimension

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